The present invention relates to an architecture and/or method for implementing a frequency detector generally and, more particularly, to a method and/or architecture for implementing a data frequency detector.
Frequency detectors are used in analog phase-locked loops for data recovery, clock recovery and frequency synthesis applications. One conventional approach for implementing a frequency detector may be found in an ISSCC99 article entitled xe2x80x9cA 1 Gb/s CMOS Clock and Data Recovery Circuitxe2x80x9d by Hui Wang, Richard Nottenburg which is hereby incorporated by reference in its entirety.
FIG. 1 illustrates an example of a conventional frequency detector 10. The frequency detector 10 has an input 11 that receives a signal DATA, an input 12 that receives a clock signal CLK and an input 13 that receives a signal QCLK. The frequency detector 10 has an output 14 that presents a signal UP and an output 15 that presents a signal DN. FIG. 2 illustrates a timing diagram of the conventional frequency detector of FIG. 1 illustrating a signal DATA, a signal CLK and a signal QCLK. A number of quadrants I, II, III and IV are defined between a number of vertical lines 16a-16e. For example, quadrant I is defined as the time between the vertical line 16b and 16c. Quadrants II, III and IV are similarly defined. A lock window is defined as a time between the vertical line 16c and the vertical line 16e. 
The quadrants are defined such that, during a particular quadrant, the signal CLK is generally at either a logic high or a logic low and the signal QCLK is at either a logic high or a logic low. Therefore, the vertical lines 16a-16e generally occur at the transitions of the signals CLK and QCLK.
In general, the signal QCLK is 90 degrees out of phase with the signal CLK. The four quadrants generally represent the various combinations of a digital high (e.g., a xe2x80x9c1xe2x80x9d) and a digital low (e.g., a xe2x80x9c0xe2x80x9d) of the signal CLK and the signal QCLK. For example, in the quadrant I, the signal CLK is low and the signal QCLK is high. In the quadrant II, the signal CLK is low and the signal QCLK is low. In the quadrant III, the signal QCLK is low and the signal CLK is high. In the quadrant IV, the signal QCLK is high and the signal CLK is high. The particular polarities of the high and low signals can be inverted. However, with the two signals CLK and QCLK operating at 90 degrees out of phase, only four possible combinations can be implemented. The four illustrated quadrants represent the four various combinations of the signal CLK and the signal QCLK. The signal DATA is shown having a transition 18 and a transition 20. The transition 18 generally occurs in one of the four quadrants (shown in the quadrant III in FIG. 2, where the signal CLK is high and the signal QCLK is low). When the data transition 18 occurs in the quadrant I or the quadrant IV, a lock condition may be present.
Referring to FIG. 3, a state machine 20 is shown implementing the various transitions of the timing diagram of FIG. 1. The state machine 20 comprises a xe2x80x9cresetxe2x80x9d state 22, an xe2x80x9cupxe2x80x9d state 24 and a xe2x80x9cdownxe2x80x9d state 26. The state machine 20 transitions between the reset state 22 and the down state 26 during (i) a transition between quadrant II and quadrant III or (ii) a transition between quadrant I and quadrant II. The reset state 22 transitions to the up state 24 during (i) the transition between quadrant IV and quadrant III or (ii) a transition between quadrant III and quadrant II. The states 24 and 26 transition back to the reset state 22 during (i) a transition between quadrant I and III (or vice versa), (ii) a transition between quadrant II and IV (or vice versa), (iii) quadrant I or (iv) quadrant IV. The state machine 20 requires the state 24 and the state 26 to transition back to the reset state 22 after each transition.
The state machine 20 transitions to a next state 24 or 26 in response to present transitions between quadrants. The state machine 20 does not use information available in the form of a current state during a transition between two quadrants. Furthermore, the state machine 20 does not check transitions between quadrants II and III due to jitter. The state machine 20 can only transition between the states 22 and 24 or the states 22 and 26.
Conventional frequency detectors implemented with the state machine 20 have a number of drawbacks including (i) leaving unused states, (ii) having next state logic that only depends on a present transition, (iii) a failure to use information available in the form of a current state and/or (iv) a failure to check transitions between particular quadrants (e.g., II and III) due to jitter.
The present invention concerns a circuit comprising a first circuit and a state machine. The first circuit may be configured to generate a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from the first clock signal, and (iii) a data signal. The state machine may be configured to generate a pump up signal and a pump down signal in response to (i) said data signal and (ii) a plurality of quadrants defined by a number of possible combinations of the state inputs. The state machine may be further configured to transition between any of the quadrants.
The objects, features and advantages of the present invention include providing a method and/or architecture to implement a frequency detector that may (i) improve the gain of the frequency detection, (ii) decrease PLL lock time and/or (iii) increase jitter tolerance.